1. Technical Field
Various embodiments generally relate to a semiconductor device, a memory system including the same, and operating method thereof, and more particularly, to a semiconductor device of which a write operation is improved by a program and verify operation, a memory system including the same, and operating method thereof.
2. Related Art
During a write operation for a memory cell, a plurality of programming operations and verifying operations may be performed in order to accurately write data to the memory cell.
With multi-level cells two or more bits may be stored therein. Thus, creating a program condition suitable for this type of memory cell is difficult. The difficulties in creating a suitable program condition are due to characteristic changes of the cells and/or characteristic differences between the cells.
FIG. 1 is a flowchart illustrating a programming and verifying operation in a conventional semiconductor device.
Referring to FIG. 1, first, a program condition corresponding to the logic level of data to be written to a cell may be loaded at step S10.
Then, at step S20, the cell may be programmed according to a program condition. Next, at step S30, a resistance value of the corresponding cell may be read.
Then, at step S40, whether the resistance value of the corresponding cell is included in a target value may be verified. The target value may be given as a predetermined range defined by a minimum value and a maximum value.
When the resistance value is included in the target value, the operation may be ended. Otherwise, the program condition may be modified at step S50, and the program operation at step S20 may be performed again.
When the write operation is performed through a plurality of programming and verifying operations, it may take a relatively long time to perform the write operation.
FIGS. 2 and 3 are diagrams for explaining a problem which may occur when a read request is inputted during a write operation.
Referring now to FIG. 2, when a read request is inputted while a write operation is performed through a plurality of program and verify operations as illustrated in FIG. 2 (i.e., P1 and V1, P2 and V2, P3 and V3, and P4 and V4), a read operation (i.e., R) may be performed after the write operation has ended. In this case, since a waiting time (i.e., Delay) for the read request is required until the write operation is completed, the performance may be degraded by the waiting time.
Furthermore, referring now to FIG. 3, a programming and verifying operation which has been already performed for a write operation (i.e., Write Operation 1-1) may be ignored (i.e., cancel), and the write operation (i.e., Write Operation 1-2) may be restarted from the beginning after a read request (i.e., R) is processed. In this case, the performance may be degraded by the time required for performing the ignored program and verify operation (i.e., Write Operation 1-1).